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ordering number : enn7109 o0503as (ot) no. 7109-1/11 overview the LB11826 is a three-phase brushless motor driver that is optimal for driving drum and paper feed motors in laser printers and plain paper copiers. this ic adopts a direct pwm drive technique for minimal power loss. flexible control of motor speed in response to an externally provided clock frequency (corresponding to the fg frequency) can be implemented by using the LB11826 in conjunction with the sanyo lb11825m. functions and features ? three-phase bipolar drive (30 v, 2.5 a) ? direct pwm drive ? built-in low side inductive kickback absorbing diode ? speed discriminator + p ll speed control ? speed locked state detection output ? built-in forward/reverse switching circuit ? full complement of built-in protection circuits, including current limiter circuit, thermal protection circuit, and motor constraint protection circuit. package dimensions unit: mm 3147b-dip28h 1 14 28 15 0.4 0.6 4.0 4.0 27.0 20.0 r1.7 8.4 1.93 1.78 1.0 12.7 11.2 sanyo: dip28h [LB11826] LB11826 sanyo electric co.,ltd. semiconductor company tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan three-phase brushless motor driver for oa products monolithic digital ic any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircrafts control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein. parameter symbol conditions ratings unit supply voltage v cc max 30 v output current i o max t 500 ms 2.5 a allowable power dissipation 1 pd max1 independent ic 3 w allowable power dissipation 2 pd max2 when infinitely large heat sink 20 w operating temperature topr C20 to +80 c storage temperature tstg C55 to +150 c specifications absolute maximum ratings at ta = 25c
no. 7109- 2 /11 LB11826 parameter symbol conditions ratings unit supply voltage range 1 v cc 9.5 to 28 v voltage output current i reg 0 to C 30 ma ld output current ild 0 to 15 ma absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit min typ max supply current 1 i cc 1 23 30 ma supply current 2 i cc 2 when stopped 3.5 5 ma [output block] output saturation voltage 1 v o sat1 i o = 1.0 a, v o (sink)+ v o (source) 2.0 2.5 v output saturation voltage 2 v o sat2 i o = 2.0 a, v o (sink)+ v o (source) 2.6 3.2 v output leakage current i o leak 100 a lower side diode forward voltage 1 vd1 id = C1.0 a 1.2 1.5 v lower side diode forward voltage 2 vd2 id = C2.0 a 1.5 2.0 v [5 v voltage output] output voltage vreg i o = C5 ma 4.65 5.00 5.35 v voltage regulation ? vreg1 v cc = 9.5 to 28 v 30 100 mv load regulation ? vreg2 i o = C5 to C20 ma 20 100 mv [hall amplifier] input bias current ihb C2 C0.5 a common-mode input voltage range vicm 1.5 vregC1.5 v hall input sensitivity 80 mv p-p hysteresis ? v in 15 24 42 mv input voltage low ? high vslh 12 mv input voltage high ? low vshl C12 mv [pwm oscillator circuit] output h level voltage v oh (pwm) 2.5 2.8 3.1 v output l level voltage v ol (pwm) 1.2 1.5 1.8 v oscillator frequency f(pwm) c = 3900 pf 18 khz amplitude v(pwm) 1.05 1.30 1.55 v p-p [csd circuit] operating voltage v oh (csd) 3.6 3.9 4.2 v external c charging current ichg C17 C12 C9 a operating time t(csd) c = 10 f design target value * 3.3 s [current limiter operation] limiter vrf v cc Cvm 0.45 0.5 0.55 v [thermal shutdown operation] thermal shutdown operating temperature tsd design target value * (junction temperature) 150 180 c hysteresis ? tsd design target value * (junction temperature) 50 c [fg amplifier] input offset voltage vio(fg) C10 +10 mv input bias current ib(fg) C1 +1 a output h level voltage v oh (fg) ifgo = C0.2 ma vregC1.2 vregC0.8 v output l level voltage v ol (fg) ifgo = 0.2 ma 0.8 1.2 v fg input sensitivity gain: 100 3 mv schmitt amplitude for the next stage design target value * 100 180 250 mv operating frequency range 2 khz open-loop gain f(fg) = 2 khz 45 51 db electrical characteristics at ta = 25 c, v cc = vm = 24 v continued on next page. note: * these are design target values and are not tested.
no. 7109- 3 /11 LB11826 parameter symbol conditions ratings unit min typ max [speed discriminator] output h level voltage v oh (d) ido = C0.1 ma vregC1.0 vregC0.7 v output l level voltage v ol (d) ido = 0.1 ma 0.8 1.1 v number of counts 512 [pll output] output h level voltage v oh (p) ipo = C0.1 ma vregC1.8 vregC1.5 vregC1.2 v output l level voltage v ol (p) ipo = 0.1 ma 1.2 1.5 1.8 v [lock detection] output l level voltage v ol (ld) ild = 10 ma 0.15 0.5 v lock range 6.25 % [integrator] input bias current ib(int) C0.4 +0.4 a output h level voltage v oh (int) iinto = C0.2 ma vregC1.2 vregC0.8 v output l level voltage v ol (int) iinto = 0.2 ma 0.8 1.2 v open-loop gain f(int) = 1 khz 45 51 db gain width product design target value * 450 khz reference voltage design target value * C5% vreg/2 5% v [clock input pin] operating frequency range f osc 1 mhz l level pin voltage v oscl i osc = C0.5 ma 1.55 v h level pin current i osch v osc = v oscl +0.5 v 0.4 ma [start/stop pin] h level input voltage range v ih (s/s) 3.5 vreg v l level input voltage range v il (s/s) 0 1.5 v input open voltage v io (s/s) vregC0.5 vreg v hysteresis ? v in 0.35 0.50 0.65 v h level input current i ih (s/s) v(s/s) = vreg C10 0 +10 a l level input current i il (s/s) v(s/s) = 0 v C280 C210 a [forward/reverse pin] h level input voltage range v ih (f/r) 3.5 vreg v l level input voltage range v il (f/r) 0 1.5 v input open voltage v io (f/r) vregC0.5 vreg v hysteresis ? v in 0.35 0.50 0.65 v h level input current i ih (f/r) v(f/r) = vreg C10 0 +10 a l level input current i il (f/r) v(f/r) = 0 v C280 C210 a continued from preceding page. note: * these are design target values and are not tested.
no. 7109- 4 /11 LB11826 truth table source f/r = "l" f/r = "h" sink in1 in2 in3 in1 in2 in3 1 out2 ? out1 h l h l h l 2 out3 ? out1 h l l l h h 3 out3 ? out2 h h l l l h 4 out1 ? out2 l h l h l h 5 out1 ? out3 l h h h l l 6 out2 ? out3 l l h h h l 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 p out int out v cc xo xi csd pwm vreg vm gnd2 gnd1 out3 out2 out1 f/r in3+ in3- in2+ in2- in1+ in1- s/s d out top view int in fg in + fg out ld fg in - LB11826 pin assignment infinitely large heat sink with no heat sink allowable power dissipation, pdmaxw ambient temperature, ta c the relation between the clock frequency, fclk, and the fg frequency, ffg, is given by the following equation. ffg(servo) = fclk/ = fclk/512
equivalent circuit block diagram and peripheral circuits no. 7109- 5 /11 LB11826 speed discrimina t or
no. 7109- 6 /11 LB11826 pin no. pin function equivalent circuit 8 300 1 k v reg 300 5 1 3 2 28 v cc vm 7 200 2 k v reg pin description motor drive output pin connect the schottky diode between the output C v cc . 28 1 2 out1 out2 out3 output gnd pin 3 gnd2 power and output current detection pins of the output. connect a low resistance (rf) between this pin and v cc . the output current is limited to the current value set with i out = vrf/rf. 5 vm stabilized power supply output pin (5 v output) connect a capacitor (about 0.1 f) between this pin and gnd for stabilization 6 vreg power pin (other than the output) 4 v cc pin to set the pwm oscillation frequency. connect a capacitor between this pin and gnd. this can be set to about 18 khz with c =3900 pf. 7 pwm pin to set the operation time of motor lock protection circuit. connection of a capacitor (about 10 f) between csd and gnd can set the protection operation time of about 3.3seconds. 8 csd continued on next page. 6 v cc
pin no. pin function equivalent circuit no. 7109- 7 /11 LB11826 p out 13 300 v reg 12 300 v reg 11 v reg pwm comparator 40 k 10 9 v reg continued from preceding page. clock input pin, which enters the clock signal (1 mhz or less) to the xi pin via resistor (about 5.1 k ). keep the xo pin open. 9 10 xi xo integrating amplifier output (speed control pin). 11 int out integrating amplifier input pin 12 int in pll output pin 13 continued on next page.
no. 7109- 8 /11 LB11826 continued from preceding page. pin no. pin function equivalent circuit speed discriminator output. accelerate: high, decelerate: low 14 dout 14 300 v reg 16 v reg 40 k 15 v reg speed lock detection output. l when the motor speed is within the speed lock range ( 6.25%). voltage resistance 30 vmax 15 ld 300 fg reset 300 17 18 v reg 20 k 20 k 2 k 19 v reg 22 k fg amplifier input pin. connection of a capacitor (about 0.1 f) between fgin and gnd causes initial reset to the logic circuit. start/stop control pin. low: 0 v to 1.5 v high: 3.5 v to vreg h level when open. hysteresis width about 0.5 v 17 fg in C 18 fg in + 19 s/s fg amplifier output pin 16 fg out continued on next page.
no. 7109- 9 /11 LB11826 overview of the LB11826 1. speed control circuit this ic performs speed control by using both the speed discriminator circuit and pll circuit. the speed control circuit outputs the error signal once for every two cycles of fg (one fg cycle counted). the pll circuit outputs the phase error signal once for each cycle of fg. as the fg servo frequency is calculated as follows, the motor speed is set with the number of fg pulses and clock frequency. f fg (servo) = f clk /512 f clk : clock frequency this ic achieves variable speed control with ease when combined with lb11825m. 2. output drive circuit this ic employs a direct pwm drive method to minimize the power loss at output. the output tr is always saturated at on, and the motor drive force is adjusted through change of the duty at which the output is turned on. since the output pwm switching is made with the lower-side output tr, it is necessary to connect the schottky diode between out and v cc (because the through current flows at an instant when the lower-side tr is turned on if the diode with a short reverse recovery time is not used). the diode between out and gnd is incorporated. when the large output current presents problem (waveform disturbance at kickback on the lower side), connect a commutating diode or schottky diode externally. 3. current limiting circuit the current limiting circuit performs limiting with the current determined from i = v rf /rf (v rf = 0.5 vtyp, rf: current detector resistance) (that is, this circuit limits the peak current). limiting operation includes decrease in the output on-duty to suppress the current. pin no. pin function equivalent circuit continued from preceding page. gnd pin (other than the output) 20 gnd1 2 k 27 v reg 22 k 300 300 22 24 26 21 23 25 v reg hall amplifier input. in+ > inC is the input high state, and the reverse is the input low state. it is recommended that the hall signal has an amplitude of 100m vp-p (differential) or more. connect a capacitor between the in+ and inC inputs if there is noise in the hall sensor signals. 22 21 24 23 26 25 in1+ in1C in2+ in2C in3+ in3C forward/reverse control pin low: 0 v to 1.5 v high: 3.5 v to vreg h level when open hysteresis width about 0.5 v 27 f/r
no. 7109- 10 /11 LB11826 4. power save circuit this ic enters the power save condition to decrease the current dissipation in the stop mode. in this condition, the bias current of most of circuits is cut off. even in the power save condition, the 5 v regulator output is given. 5. reference clock this is entered from the external signal source (1 mhz max) via a resistor (reference: about 5.1 k ) in series with the xi pin. the xo pin is left open. input signal source levels: low-level voltage: 0 to 0.8 v high-level voltage: 2.5 to 5.0 v 6. speed lock range the speed lock range is 6.25% of the constant speed. if the motor speed falls inside the lock range, the ld pin goes to l (open collector output). when the motor speed falls outside the lock range, the on-duty ratio of motor drive output changes according to the speed error, causing control to keep the motor speed within the lock range. 7. pwm frequency pwm frequency is determined from the capacity c (f) of capacitor connected to the pwm pin. f pwm ? 1/(14,400 c) it is recommended to keep the pwm frequency at 15 kC20 khz. 8. hall input signal the hall input requires the signal input with an amplitude exceeding the hysteresis width (42 mv max). considering the effect of noise, the input with the amplitude of 100 mv or more is recommended. 9. f/r changeover motor rotation direction can be changed over with the f/r pin. when changing f/r while the motor is running, pay attention to following points. ? for the through current at a time of changeover, the countermeasure is taken using a circuit. however, it is necessary to prevent exceeding of the rated voltage (30 v) due to rise of v cc voltage at a time of changeover (because the motor current returns instantaneously to the power supply). when this problem exists, increase the capacity of a capacitor between v cc and gnd. ? when the motor current exceeds the current limit value after changeover, the lower-side tr is turned off. but, the upper-side tr enters the short-brake condition and the current determined from the motor counter electromotive voltage and coil resistance flows. it is necessary to prevent this current from exceeding the rated current (2.5 a). (f/r changeover at high motor speed is dangerous.) 10. motor lock protection circuit a motor lock protection circuit is incorporated for protection of ic and motor when the motor is locked. when the ld output is h (unlocked) for a certain period in the start condition, the lower-side tr is turned off. this time is set with the capacity of the capacitor connected to the csd pin. the time can be set to about 3.3 seconds with the capacity of 10 f (variance about 30%). set time (s) ? 0.33 c ( f) when the capacitor used has a leak current, due consideration is necessary because it may cause error in the set time, etc. cancelling requires either the stop condition or re-application of power supply (in the stop condition). when the lock protection circuit is not to be used, connect the csd pin to gnd. when the stop period during which lock protection is to be cancelled is short, the charge of capacitor cannot be discharged completely and the lock protection activation time at restart becomes shorter than the set value. it is necessary to provide the stop time with an allowance while referring to the following equation. (the same applies to restart in the motor start transient condition.) stop time (ms) 3 15 c ( f)
ps no. 7109- 11 /11 LB11826 this catalog provides information as of october, 2003. specifications and information herein are subject to change without notice. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customers products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customers products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the delivery specification for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. 11. power supply stabilization this ic has a large output current and is driven by switching, resulting in ready oscillation of the power line. it is therefore necessary to connect a capacitor with a sufficient capacity between the vcc pin and gnd for stabilization. when a diode is inserted in the power line to prevent breakdown due to reverse connection of power supply, the power line is particularly readily oscillated. the larger capacity need be selected. 12. constant of integrating amplifier parts arrange the integrating amplifier external parts as near as possible to ic to protect them from noise effects. arrange them by keeping the largest possible distance from the motor.

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